module rx(clk,rst,h1_sig,Rx_pin_in,bps_clk,Rx_en,idle_sig,end_sig,rx_data);
input clk,rst;
input h1_sig;							//起始标志位
input Rx_pin_in;
input bps_clk;							//16倍频波特率
input Rx_en;							//使能
output idle_sig,end_sig;			//空闲标志位,结束标志位
output [7:0] rx_data;				//接收数据
reg [3:0] i;
reg [7:0] data=0;
reg count=0;
reg done=0;

always @(posedge clk or negedge rst)
begin
    if(!rst)
	 begin
	     i<=3'd0;
		  data<=8'd0;
		  count<=0;
		  done<=0;
	 end
	 else if(Rx_en)
			case(i)
		          4'd0:if(h1_sig) begin i<=i+1'b1; count<=1'b1; end
					 4'd1: if(bps_clk) begin i<=i+1'b1; end
					 4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9:
					 if(bps_clk) begin i<=i+1'b1; data[i-2]<=Rx_pin_in; end
					 4'd10:begin i<=i+1'b1; done<=1'b1; count<=1'b0; end
					 4'd11:begin i<=4'd0; done<=1'b0; end
			endcase
end

assign idle_sig=count;
assign rx_data=data;
assign end_sig=done;
endmodule
